LLMs Automate Hardware Verification Heuristic Evolution with IC3-Evolve

The performance of hardware safety model checking, particularly using algorithms like IC3 (Property-Directed Reachability), has historically been constrained by the intricate and often manually tuned heuristics that govern its operation. This manual optimization process is not only costly and time-consuming but also prone to brittleness and reproducibility challenges. The introduction of IC3-Evolve marks a significant advancement by leveraging large language models (LLMs) to automate the evolution of these critical heuristics, promising to enhance the efficiency and reliability of hardware verification processes.

IC3-Evolve operates as an automated offline code-evolution framework, utilizing an LLM to propose small, auditable patches to an IC3 implementation. A crucial innovation is its proof-/witness-gated validation mechanism: every candidate patch must either generate a checkable inductive invariant for SAFE runs or a replayable counterexample trace for UNSAFE runs. This stringent correctness gating prevents the deployment of unsound edits, ensuring the integrity of the verification process. Furthermore, because the LLM is used exclusively offline, the resulting evolved checker functions as a standalone artifact, incurring zero ML/LLM inference overhead and eliminating runtime model dependencies, a key requirement for industrial adoption.

This methodology has been successfully evaluated on the public Hardware Model Checking Competition (HWMCC) benchmark and demonstrated generalizability across unseen public and industrial benchmarks. The ability of IC3-Evolve to reliably discover practical heuristic improvements under strict correctness gates suggests a pathway to significantly accelerate hardware design cycles and bolster the reliability of complex systems. This approach holds promise for broader application in formal verification, potentially transforming how critical software and hardware are developed and validated.