PolyBlocks: A Compiler Infrastructure for AI Chips and Frameworks

PolyBlocks presents a modular and reusable compiler infrastructure designed to facilitate the development of high-performance code for AI programming frameworks and AI chips. Built on MLIR, PolyBlocks utilizes pass pipelines to compose transformations on loop nests and SSA, leveraging lightweight affine access analysis. The infrastructure supports a range of optimizations, including multi-level tiling, fusion, on-chip scratchpad usage, and mapping matmuls and convolutions to matrix units. The design emphasizes reusability, enabling the creation of compilers for new chips while leveraging existing infrastructure. Experimental results demonstrate that PolyBlocks-powered just-in-time compilation for PyTorch and JAX can match or outperform Torch Inductor and XLA in certain scenarios. While PolyBlocks shows promise, further development and optimization are necessary to consistently surpass vendor-tuned libraries and hand-written kernels. The potential impact of PolyBlocks lies in its ability to accelerate the deployment of AI applications on diverse hardware platforms by simplifying the compiler development process and enabling automatic code generation.

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